PCB design for high performance product has become expensive and difficult in the PCB placement and wiring phase. The detail design phase need to meet multiple aspects such as:
– High frequency clock with SI/PI
– Three-dimensional mounting
– High pin count with CSP in extreme narrow pitch
Design Force provides a variety of functions and environment required for high-speed circuit design. Product line up supports ideas, for example, built-in transmission line SI simulator, automatic routing with multiple strategy settings, FPGA design flow with software integration, easy of package design with hierarchical boards under the multi-board design environment. Zuken is also collaborating with FPGA vendors and semiconductor vendors, or CAE vendors in which every designer can have the latest devices support and easy-to-use environment.
This time, we will introduce the three new features of high speed circuit design among those features.
(1) Zigzag Routing Function in any angle
Routing direction of the differential pair may cause delay when glass fiber in the board is laid horizontally or vertically to the routing pattern. Difference in positioning of 2 patterns, 1 pattern directly above glass fiber and another over the epoxy, results in having difference in dielectric constant and this small difference may cause delay in 1 of the signal.
In order to avoid this phenomenon, in the reference guide provided by the chip vendors and FPGA vendors, high-speed differential pair signal is to be routed at an angle so that there will be uniform influence from the glass fibre to the pattern. This is where zigzag routing becomes handy.
Without the support of Zigzag routing function, it is difficult to route patterns in this manner. In Design Force, it is easy and possible to route in zigzag shape, and easy to follow instruction provided from chip venders to solve this delay problem in differential pair routing.
- Reduce the critical delay condition of differential pair signal.
- Zigzag shape can be created with simple command.
(2)Differential Pair Routing
For high immunity to external noise in high speed transmission, many of the high-speed operating devices have adopted differential pair interface.
In order to utilize the characteristic of differential pair interface, it needs a complicated operation to perform the routing, and there are limitations with conventional routing operation command.
In compliance with the rules defined in the differential signal, it route like the normal single line except that it is wired in pair.
Pin pair pattern length guide
Report the measured value and the pattern length rules in real time.
Routing clearance gap display
Checking the clearance gap of a closed obstacle during wire route is possible
Switching of the reference point
Choose reference point from positive/negative/center of the differential pair.
- Differential pair routing command helps to easily route differential patterns in the similar manner as you route a single pattern.
- With pin pair pattern length guide and the pattern clearance gap display function, it helps to navigate designer to route with better visibility over the constraints rules.
- Differential pair routing command maintains assigned clearance between pin pair patterns.
(3) Pinpair Route Report
In order to guarantee the operation of high speed device, width and length constraint of wiring need to be maintain for the quality of the signal. Besides, the conventional pin pair route report capabilities, Design Force has added the wire width report capabilities which helps to understanding detail of pattern layout.
- Grasp the overview of pattern layout that contribute to the quality of the signal from an accurate report.
- Easily review by cross probing between the table and pin-pair segment in the canvas for review.